1. Field of the Invention
The invention relates to communications between integrated circuits and more specifically to data transfer and coherency in a multi-node or multi-processor system.
2. Description of the Related Art
Processors and caches have existed since shortly after the advent of the computer. However, the move to using multiple processors has posed new challenges. Previously, data existed in one place (memory for example) and might be copied into one other place (a cache for example). Keeping data coherent between the two possible locations for the data was a relatively simple problem. Utilizing multiple processors, multiple caches may exist, and each may have a copy of a piece of data. Alternatively, a single processor may have a copy of a piece of data which it needs to use exclusively.
Difficulties in multi-processor systems may arise when the system sends data to the input/output (I/O) subsystems. A multi-processor system may be optimized for transfer of small amounts of data between a processor and memory. Such data transfers may be done on an ongoing basis, and have well-known tendencies toward temporal and spatial (address) locality. However, data transfers to and from I/O subsystems tend to be less frequent and have larger size. Moreover, data transfers between processors and I/O subsystems also tend to have different locality characteristics, if they have any characteristics at all. Thus, handling data transfers between processors and I/O subsystems in multi-processor systems may be a useful ability.